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» A Time Predictable Instruction Cache for a Java Processor
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PLDI
2004
ACM
14 years 2 months ago
Inducing heuristics to decide whether to schedule
Instruction scheduling is a compiler optimization that can improve program speed, sometimes by 10% or more—but it can also be expensive. Furthermore, time spent optimizing is mo...
John Cavazos, J. Eliot B. Moss
PDPTA
2004
13 years 10 months ago
Static Performance Evaluation for Memory-Bound Computing: The MBRAM Model
We present the MBRAM model for static evaluation of the performance of memory-bound programs. The MBRAM model predicts the actual running time of a memory-bound program directly fr...
Gene Cooperman, Xiaoqin Ma, Viet Ha Nguyen
JILP
2000
90views more  JILP 2000»
13 years 8 months ago
Speculative Updates of Local and Global Branch History: A Quantitative Analysis
In today's wide-issue processors, even small branch-misprediction rates introduce substantial performance penalties. Worse yet, inadequate branch prediction creates a bottlen...
Kevin Skadron, Margaret Martonosi, Douglas W. Clar...
ASPLOS
2006
ACM
14 years 2 months ago
A performance counter architecture for computing accurate CPI components
Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaini...
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, J...
ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
14 years 26 days ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy