264 search results - page 43 / 53 » A Time Predictable Instruction Cache for a Java Processor |
MICRO
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
ISCA
1997
IEEE
14 years 24 days ago
1997
IEEE
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
CODES
2001
IEEE
14 years 7 days ago
2001
IEEE
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
CODES
2004
IEEE
14 years 10 days ago
2004
IEEE
The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing th...
CF
2010
ACM
14 years 1 months ago
2010
ACM
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...