264 search results - page 8 / 53 » A Time Predictable Instruction Cache for a Java Processor |
RTSS
2008
IEEE
14 years 3 months ago
2008
IEEE
With the advent of increasingly complex hardware in realtime embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), ...
VLDB
1999
ACM
14 years 29 days ago
1999
ACM
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
MICRO
2002
IEEE
13 years 8 months ago
2002
IEEE
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
MICRO
2002
IEEE
14 years 1 months ago
2002
IEEE
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
APCSAC
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...