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» A Variation Aware High Level Synthesis Framework
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ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
14 years 16 days ago
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...
ASPDAC
2009
ACM
122views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Tolerating process variations in high-level synthesis using transparent latches
—Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced...
Yibo Chen, Yuan Xie
ATS
2010
IEEE
229views Hardware» more  ATS 2010»
13 years 5 months ago
Variation-Aware Fault Modeling
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
Fabian Hopsch, Bernd Becker, Sybille Hellebrand, I...
PDP
2007
IEEE
14 years 1 months ago
A High-Level Reference Model for Reusable Object-Level Coordination Support in Groupware Applications
The success of groupware software largely depends on its capability for being reused in different collaborative scenarios without requiring significant software development effort...
Miguel A. Gomez-Hernandez, Juan I. Asensio-P&eacut...
PRDC
2006
IEEE
14 years 1 months ago
SEVA: A Soft-Error- and Variation-Aware Cache Architecture
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai