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» A Visual Approach to Validating System Level Designs
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ISSS
2002
IEEE
144views Hardware» more  ISSS 2002»
14 years 15 days ago
A Visual Approach to Validating System Level Designs
This paper proposes a simulation-based methodology for validation of a system under design in an early phase of development. The key element of this approach is the visual speciļ¬...
Jürgen Ruf, Thomas Kropf, Jochen Klose
TCAD
2010
121views more  TCAD 2010»
13 years 2 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
ISPW
2006
IEEE
14 years 1 months ago
Automated Recognition of Low-Level Process: A Pilot Validation Study of Zorro for Test-Driven Development
Abstract. Zorro is a system designed to automatically determine whether a developer is complying with the Test-Driven Development (TDD) process. Automated recognition of TDD could ...
Hongbing Kou, Philip M. Johnson
MTV
2005
IEEE
128views Hardware» more  MTV 2005»
14 years 1 months ago
Automated Extraction of Structural Information from SystemC-based IP for Validation
The increasing complexity and size of system level design models introduces a diļ¬ƒcult challenge for validating them. Hence, in most industries, design validation takes a large p...
David Berner, Hiren D. Patel, Deepak Mathaikutty, ...
ISSS
2002
IEEE
124views Hardware» more  ISSS 2002»
14 years 15 days ago
A New Performance Evaluation Approach for System Level Design Space Exploration
Application speciļ¬c systems have potential for customization of design with a view to achieve a better costperformance-power trade-oļ¬€. Such customization requires extensive de...
M. Balakrishnan, Anshul Kumar, C. P. Joshi