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» A Visual Approach to Validating System Level Designs
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ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
14 years 1 months ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
GECCO
2004
Springer
136views Optimization» more  GECCO 2004»
14 years 2 months ago
System Level Hardware-Software Design Exploration with XCS
Abstract. The current trend in Embedded Systems (ES) design is moving towards the integration of increasingly complex applications on a single chip. An Embedded System has to satis...
Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciu...
TVLSI
2008
152views more  TVLSI 2008»
13 years 8 months ago
MMV: A Metamodeling Based Microprocessor Validation Environment
With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validati...
Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Di...
HICSS
2007
IEEE
124views Biometrics» more  HICSS 2007»
14 years 3 months ago
POSAML: A Visual Modeling Framework for Middleware Provisioning
Effective provisioning of next generation distributed applications hosted on diverse middleware platforms incurs significant challenges due to the applications’ growing complex...
Dimple Kaul, Arundhati Kogekar, Aniruddha S. Gokha...
SOCO
2010
Springer
13 years 7 months ago
Visualizing and Assessing a Compositional Approach of Business Process Design
Abstract. In the context of Services Oriented Architecture (Soa), complex systems are realized through the design of business–driven processes. Since the design of a complete pro...
Sébastien Mosser, Alexandre Bergel, Mireill...