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CEC
2005
IEEE
14 years 2 months ago
FPGA segmented channel routing using genetic algorithms
A genetic algorithm approach for segmented channel routing in field programmable gate arrays (FPGA's) is presented in this paper. The FPGA segmented channel routing problem (F...
Lipo Wang, Lei Zhou, Wen Liu
DATE
2000
IEEE
85views Hardware» more  DATE 2000»
14 years 24 days ago
Meeting Delay Constraints in DSM by Minimal Repeater Insertion
We address the problem of inserting repeaters, selected from a library, at feasible locations in a placed and routed network to meet user-specified delay constraints. We use mini...
I-Min Liu, Adnan Aziz, D. F. Wong
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
14 years 24 days ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
14 years 1 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
NECO
2010
101views more  NECO 2010»
13 years 3 months ago
Large-Margin Classification in Infinite Neural Networks
We introduce a new family of positive-definite kernels for large margin classification in support vector machines (SVMs). These kernels mimic the computation in large neural netwo...
Youngmin Cho, Lawrence K. Saul