228 search results - page 16 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
DAC
2002
ACM
14 years 9 months ago
2002
ACM
This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we devel...
GLVLSI
2010
IEEE
14 years 1 months ago
2010
IEEE
In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other wo...
DFT
1999
IEEE
14 years 27 days ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
FPGA
2006
ACM
14 years 7 days ago
2006
ACM
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
DAC
1999
ACM
14 years 9 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...