127 search results - page 1 / 26 » A cache-defect-aware code placement algorithm for improving ... |
127
Voted
ICCAD
2005
IEEE
15 years 11 months ago
2005
IEEE
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
150
Voted
CASES
2010
ACM
15 years 22 days ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
134
Voted
PLDI
2005
ACM
15 years 8 months ago
2005
ACM
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...
142
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CLUSTER
2001
IEEE
15 years 6 months ago
2001
IEEE
In this paper we report experiences on a parallel implementation of a standard cell placement algorithm on a cluster of myrinet connected PCs. The proposed algorithm is based on a...
153
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ISHPC
2003
Springer
15 years 8 months ago
2003
Springer
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...