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» A cis-regulatory logic simulator
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IPPS
2006
IEEE
14 years 5 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
IPPS
2006
IEEE
14 years 5 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
LICS
2006
IEEE
14 years 4 months ago
On the Expressiveness of Linearity vs Persistence in the Asychronous Pi-Calculus
We present an expressiveness study of linearity and persistence of processes. We choose the π-calculus, one of the main representatives of process calculi, as a framework to cond...
Catuscia Palamidessi, Vijay A. Saraswat, Frank D. ...
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
14 years 4 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
RTAS
2006
IEEE
14 years 4 months ago
Scalable Modeling and Performance Evaluation of Wireless Sensor Networks
A notable features of many proposed Wireless Sensor Networks (WSNs) deployments is their scale: hundreds to thousands of nodes linked together. In such systems, modeling the state...
YoungMin Kwon, Gul Agha