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» A cis-regulatory logic simulator
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FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
14 years 2 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
14 years 2 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
ASPLOS
2010
ACM
14 years 2 months ago
Butterfly analysis: adapting dataflow analysis to dynamic parallel monitoring
Online program monitoring is an effective technique for detecting bugs and security attacks in running applications. Extending these tools to monitor parallel programs is challeng...
Michelle L. Goodstein, Evangelos Vlachos, Shimin C...
ASPDAC
2005
ACM
93views Hardware» more  ASPDAC 2005»
14 years 26 days ago
Power minimization for dynamic PLAs
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, ...
BIOCOMP
2007
14 years 10 days ago
Stability Analysis of Genetic Regulatory Network with Additive Noises
Background: Genetic regulatory networks (GRN) can be described by differential equations with SUM logic which has been found in many natural systems. Identification of the network...
Yufang Jin