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» A comparative study of power efficient SRAM designs
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JCP
2008
160views more  JCP 2008»
13 years 7 months ago
A Bluetooth-based Sensor Node for Low-Power Ad Hoc Networks
TCP/IP has recently taken promising steps toward being a viable communication architecture for networked sensor nodes. Furthermore, the use of Bluetooth can enable a wide range of ...
Jens Eliasson, Per Lindgren, Jerker Delsing
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
14 years 1 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
TWC
2008
154views more  TWC 2008»
13 years 7 months ago
MEERA: Cross-Layer Methodology for Energy Efficient Resource Allocation in Wireless Networks
Abstract-- In many portable devices, wireless network interfaces consume upwards of 30% of scarce system energy. Reducing the transceiver's power consumption to extend the sys...
Sofie Pollin, Rahul Mangharam, Bruno Bougard, Lies...
ARITH
2007
IEEE
14 years 2 months ago
Performing Advanced Bit Manipulations Efficiently in General-Purpose Processors
This paper describes a new basis for the implementation of a shifter functional unit. We present a design based on the inverse butterfly and butterfly datapath circuits that perfo...
Yedidya Hilewitz, Ruby B. Lee
MICRO
2000
IEEE
95views Hardware» more  MICRO 2000»
13 years 11 months ago
Very low power pipelines using significance compression
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
Ramon Canal, Antonio González, James E. Smi...