802 search results - page 92 / 161 » A comparative study of power efficient SRAM designs |
GLOBECOM
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract—We consider the distributed estimation of an unknown vector signal in a resource constrained sensor network with a fusion center. Due to power and bandwidth limitations,...
VTS
2007
IEEE
14 years 2 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
TCAD
2002
13 years 7 months ago
2002
Abstract--In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-o...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...