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» A compiled implementation of strong reduction
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CODES
2009
IEEE
13 years 8 months ago
Efficient dynamic voltage/frequency scaling through algorithmic loop transformation
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...
Mohammad Ali Ghodrat, Tony Givargis
ICS
1995
Tsinghua U.
13 years 11 months ago
Idiom Recognition in the Polaris Parallelizing Compiler
The elimination of induction variables and the parallelization of reductions in FORTRAN programs have been shown to be integral to performance improvement on parallel computers 7,...
William M. Pottenger, Rudolf Eigenmann
ISLPED
1995
ACM
70views Hardware» more  ISLPED 1995»
13 years 11 months ago
Transformation and synthesis of FSMs for low-power gated-clock implementation
We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transfor...
Luca Benini, Giovanni De Micheli
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 8 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
JFP
2002
108views more  JFP 2002»
13 years 7 months ago
A calculus with polymorphic and polyvariant flow types
We present CIL , a typed -calculus which serves as the foundation for a typed intermediate language for optimizing compilers for higher-order polymorphic programming languages. Th...
J. B. Wells, Allyn Dimock, Robert Muller, Franklyn...