34 search results - page 4 / 7 » A complete design for power methodology and flow for large A... |
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
Efficient use of an optimized memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in data ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
We present a methodology, an environment and supporting tools to map an application on a wireless sensor network (WSN). While the method is quite general, we use extensively an exa...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the lo...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...