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» A computational architecture for heterogeneous reasoning
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IPPS
2007
IEEE
14 years 3 months ago
A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
Alisson Vasconcelos De Brito, Matthias Kühnle...
DAC
1996
ACM
14 years 1 months ago
Improving the Efficiency of Power Simulators by Input Vector Compaction
Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input...
Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, ...
DAC
1994
ACM
14 years 1 months ago
Synthesis of Instruction Sets for Pipelined Microprocessors
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
Ing-Jer Huang, Alvin M. Despain
DAC
1994
ACM
14 years 14 days ago
New Techniques for Efficient Verification with Implicitly Conjoined BDDs
-- In previous work, Hu and Dill identified a common cause of BDD-size blowup in high-level design verification and proposed the method of implicitly conjoined invariants to addres...
Alan J. Hu, Gary York, David L. Dill
IPPS
2007
IEEE
14 years 3 months ago
A Peer-to-Peer Infrastructure for Autonomous Grid Monitoring
Modern grids have become very complex by their size and their heterogeneity. It makes the deployment and maintenance of systems a difficult task requiring lots of efforts from ad...
Laurent Baduel, Satoshi Matsuoka