Sciweavers

31 search results - page 3 / 7
» A configuration memory hierarchy for fast reconfiguration wi...
Sort
View
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
14 years 20 days ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
VEE
2006
ACM
178views Virtualization» more  VEE 2006»
14 years 1 months ago
Impact of virtual execution environments on processor energy consumption and hardware adaptation
During recent years, microprocessor energy consumption has been surging and efforts to reduce power and energy have received a lot of attention. At the same time, virtual executio...
Shiwen Hu, Lizy Kurian John
ESTIMEDIA
2003
Springer
14 years 24 days ago
Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems
Current multimedia applications are characterized by highly dynamic and non-deterministic behavior as well as high-performance requirements. In addition, portable devices demand a...
Javier Resano, Diederik Verkest, Daniel Mozos, Ser...
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
13 years 11 months ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
DCC
2008
IEEE
13 years 9 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...