Automatic Tuning of Two-Level Caches to Embedded Applications

The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimizations. We present an automated method for tuning two-level caches to embedded applications for reduced energy consumption. The method is applicable to both a simulation-based exploration environment and a hardwarebased system prototyping environment. We introduce the twolevel cache tuner, or TCaT - a heuristic for searching the huge solution space of possible configurations. The heuristic interlaces the exploration of the two cache levels and searches the various cache parameters in a specific order based on their impact on energy. We show the integrity of our heuristic across multiple memory configurations and even in the presence of hardware/software partitioning

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: Ann Gordon-Ross, Frank Vahid, Nikil Dutt
• Keywords: Cache, Cache Configuration, DATE 2004, Hardware, Heuristic