129 search results - page 16 / 26 » A datapath synthesis system for the reconfigurable datapath ... |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—This paper proposes a programmable geometry engine (GE) reducing the expensive internal buffers and register files of the conventional programmable GEs and sharing datapaths of ...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
EDCC
2006
Springer
13 years 11 months ago
2006
Springer
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...