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» A decoupled KILO-instruction processor
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HPCA
2003
IEEE
14 years 10 months ago
Dynamic Data Dependence Tracking and its Application to Branch Prediction
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
Lei Chen, Steve Dropsho, David H. Albonesi
ICCD
2005
IEEE
98views Hardware» more  ICCD 2005»
14 years 6 months ago
Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines
Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature managem...
Anahita Shayesteh, Eren Kursun, Timothy Sherwood, ...
MICRO
2008
IEEE
84views Hardware» more  MICRO 2008»
14 years 4 months ago
A performance-correctness explicitly-decoupled architecture
Optimizing the common case has been an adage in decades of processor design practices. However, as the system complexity and optimization techniques’ sophistication have increas...
Alok Garg, Michael C. Huang
ADC
2008
Springer
114views Database» more  ADC 2008»
14 years 4 months ago
Enabling Resource-Awareness for In-Network Data Processing in Wireless Sensor Networks
The next-generation of wireless sensor platforms allows for more advanced in-network data processing. The central challenge remains energy and communication efficiency. This paper...
Uwe Röhm, Mohamed Medhat Gaber, Quincy Tse
ISCA
2007
IEEE
162views Hardware» more  ISCA 2007»
14 years 4 months ago
BulkSC: bulk enforcement of sequential consistency
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...
Luis Ceze, James Tuck, Pablo Montesinos, Josep Tor...