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IEEEINTERACT
2002
IEEE
14 years 1 months ago
Compiling for Fine-Grain Concurrency: Planning and Performing Software Thread Integration
Embedded systems require control of many concurrent real-time activities, leading to system designs which feature multiple hardware peripherals with each providing a specific, ded...
Alexander G. Dean
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
14 years 2 months ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 2 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
VLSID
2006
IEEE
119views VLSI» more  VLSID 2006»
14 years 9 months ago
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
ECRTS
2010
IEEE
13 years 9 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller