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MSO
2003
13 years 9 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
ASPLOS
2010
ACM
13 years 11 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
CODES
2001
IEEE
13 years 11 months ago
A constraint-based application model and scheduling techniques for power-aware systems
New embedded systems must be power-aware, not just low-power. That is, they must track their power sources and the changingpower and performance constraints imposed by the environ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...
DT
2006
113views more  DT 2006»
13 years 7 months ago
A Platform-Based Taxonomy for ESL Design
the abstraction level at which designers express systems, enabling new levels of design reuse, and providing for design chain integration ool flows and abstraction levels. The purp...
Douglas Densmore, Roberto Passerone
IPPS
2006
IEEE
14 years 1 months ago
A framework to develop symbolic performance models of parallel applications
Performance and workload modeling has numerous uses at every stage of the high-end computing lifecycle: design, integration, procurement, installation and tuning. Despite the trem...
Sadaf R. Alam, Jeffrey S. Vetter