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ICIP
2007
IEEE
14 years 1 months ago
Software Pipelines Design for Variable Block-Size Motion Estimation with Large Search Range
This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, chal...
Zhigang Yang, Wen Gao, Yan Liu, Debin Zhao
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
14 years 1 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
OSDI
2008
ACM
14 years 8 months ago
SR-IOV Networking in Xen: Architecture, Design and Implementation
SR-IOV capable network devices offer the benefits of direct I/O throughput and reduced CPU utilization while greatly increasing the scalability and sharing capabilities of the devi...
Yaozu Dong, Zhao Yu, Greg Rose
ICIP
1998
IEEE
14 years 9 months ago
B-spline Snakes and a JAVA Interface: An Intuitive Tool for General Contour Outlining
We present a novel formulation for B-spline snakes that can be used as a tool for fast and intuitive contour outlining. The theory is implemented in a platform independent JAVA in...
Patrick Brigger, Robert Engel, Michael Unser
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 1 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier