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» A digit serial algorithm for the integer power operation
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ASPDAC
2007
ACM
115views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware
- This paper covers a multi-functional hardware intellectual property (IP) for the encoding and decoding of digital moving pictures with low power consumption. The IP is mainly int...
M. Hase, K. Akie, M. Nobori, K. Matsumoto
ICASSP
2011
IEEE
12 years 11 months ago
Convex approximation algorithms for back-pressure power control of wireless multi-hop networks
Cross-layer design and operation of wireless networks has attracted significant interest in the last decade, yet some basic problems in the area remain unsolved. In this paper, w...
Evaggelia Matskani, Nikos D. Sidiropoulos, Leandro...
ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
12 years 11 months ago
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level
— The last two decades have seen many efficient algorithms and architectures for the design of low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, tha...
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Pa...
CTRSA
2005
Springer
78views Cryptology» more  CTRSA 2005»
14 years 28 days ago
New Minimal Weight Representations for Left-to-Right Window Methods
For an integer w ≥ 2, a radix 2 representation is called a width-w nonadjacent form (w-NAF, for short) if each nonzero digit is an odd integer with absolute value less than 2w−...
James A. Muir, Douglas R. Stinson
FPL
2008
Springer
91views Hardware» more  FPL 2008»
13 years 9 months ago
Power efficient DSP datapath configuration methodology for FPGA
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
Stephen McKeown, Roger Woods, John McAllister