Power efficient DSP datapath configuration methodology for FPGA

Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power methodology for the design of FPGA-based, power efficient variable length DSP IP cores is presented. Commonality in the algorithm is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show the resulting architecture requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.

• Type: Conference
• Year: 2008
• Where: FPL
• Authors: Stephen McKeown, Roger Woods, John McAllister
• Keywords: Achievable Functionality, FPL 2008, Hardware, Peak Power, Peak Power Budget