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» A fast algorithm for power grid design
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ASPDAC
2008
ACM
108views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block sel
Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due t...
Jui-Yuan Hsieh, Shanq-Jang Ruan
HPDC
2007
IEEE
14 years 1 months ago
How CN and P2P technologies may help build next-generation grids
With the evolution of technology, Grids cannot be considered any more solely as a federation of a modest number of powerful cluster computers. Trends show that future Grids will i...
Guillaume Pierre
ICCAD
2009
IEEE
93views Hardware» more  ICCAD 2009»
13 years 5 months ago
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs
Power gating has been a very effective way to reduce leakage power. One important design issue for a power gating design is to limit the surge current during the wakeup process. N...
Ming-Chao Lee, Yu-Ting Chen, Yo-Tzu Cheng, Shih-Ch...
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
14 years 28 days ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
FPL
2006
Springer
125views Hardware» more  FPL 2006»
13 years 11 months ago
Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
Tom Van Court, Martin C. Herbordt