968 search results - page 64 / 194 » A faster implementation of APlace |
187
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VLSID
2007
IEEE
16 years 4 months ago
2007
IEEE
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
126
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ICCAD
2001
IEEE
16 years 28 days ago
2001
IEEE
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
135
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ISVC
2009
Springer
15 years 10 months ago
2009
Springer
The available rendering performance on current computers increases constantly, primarily by employing parallel algorithms using the newest many-core hardware, as for example multi-...
127
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ICC
2008
IEEE
15 years 10 months ago
2008
IEEE
Abstract— The design of LDPC decoders with low complexity, high throughput, and good performance is a critical task. A well-known strategy is to design structured codes such as q...
110
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FPL
2007
Springer
15 years 10 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...