7 search results - page 1 / 2 » A formal non-heuristic ATPG approach |
ATS
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract—SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduce...
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
ITC
2002
IEEE
13 years 11 months ago
2002
IEEE
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
EURODAC
1995
IEEE
13 years 10 months ago
1995
IEEE
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
MEMOCODE
2007
IEEE
14 years 26 days ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...