105 search results - page 6 / 21 » A gate resizing technique for high reduction in power consum... |
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
GLVLSI
2000
IEEE
13 years 11 months ago
2000
IEEE
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy r...
PATMOS
2010
Springer
13 years 5 months ago
2010
Springer
In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power con...