105 search results - page 9 / 21 » A gate resizing technique for high reduction in power consum... |
ICCD
2003
IEEE
14 years 5 months ago
2003
IEEE
- This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep t...
TVLSI
2010
13 years 3 months ago
2010
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particula...
FPGA
2010
ACM
14 years 5 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
VEE
2006
ACM
14 years 2 months ago
2006
ACM
During recent years, microprocessor energy consumption has been surging and efforts to reduce power and energy have received a lot of attention. At the same time, virtual executio...
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
The rate at which a digital signal processing (DSP) system operates depends on the highest frequency component in the input signal. DSP applications must sample their inputs at a ...