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DAC
1996
ACM
13 years 11 months ago
A Register File and Scheduling Model for Application Specific Processor Synthesis
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
Ehat Ercanli, Christos A. Papachristou
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
14 years 21 days ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...
TVLSI
2008
187views more  TVLSI 2008»
13 years 7 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
VLSID
2002
IEEE
174views VLSI» more  VLSID 2002»
14 years 7 months ago
Architecture Implementation Using the Machine Description Language LISA
The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design...
Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, ...
CASES
2005
ACM
13 years 9 months ago
Micro embedded monitoring for security in application specific instruction-set processors
This paper presents a methodology for monitoring security in Application Specific Instruction-set Processors (ASIPs). This is a generalized methodology for inline monitoring insec...
Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad ...