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ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
14 years 2 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
ICCAD
2007
IEEE
122views Hardware» more  ICCAD 2007»
14 years 5 months ago
Engineering change using spare cells with constant insertion
—In the VLSI design process, a design implementation often needs to be corrected because of new specifications or design constraint violations. This correction process is referre...
Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgo...
ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
14 years 11 days ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
CODES
1996
IEEE
14 years 7 days ago
Uninterpreted Co-Simulation for Performance Evaluation of Hw/Sw Systems
Performance modeling and evaluation of embedded hardware/software systems is important to help the CoDesign process. The hardware/software partitioning needs to be evaluated befor...
Jean Paul Calvez, Dominique Heller, Olivier Pasqui...
GECCO
2006
Springer
206views Optimization» more  GECCO 2006»
13 years 11 months ago
A dynamically constrained genetic algorithm for hardware-software partitioning
In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high-level lan...
Pierre-André Mudry, Guillaume Zufferey, Gia...