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ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
14 years 3 days ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw
EH
2004
IEEE
117views Hardware» more  EH 2004»
13 years 11 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
13 years 11 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm
FTCS
1998
77views more  FTCS 1998»
13 years 9 months ago
Strong Partitioning Protocol for a Multiprocessor VME System
The trend in implementing today's embedded applications is toward the use of commercial-off-the-shelf open architecture. Reducing costs and facilitating systems integration a...
Mohamed F. Younis, Jeffrey X. Zhou, Mohamed Abouta...
ICCAD
2010
IEEE
117views Hardware» more  ICCAD 2010»
13 years 6 months ago
A synthesis flow for digital signal processing with biomolecular reactions
Abstract--We present a methodology for implementing digital signal processing (DSP) operations such as filtering with biomolecular reactions. From a DSP specification, we demonstra...
Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, K...