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FPL
2006
Springer
223views Hardware» more  FPL 2006»
13 years 11 months ago
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
Carlos Morra, M. Sackmann, Sunil Shukla, Jürg...
DATE
2005
IEEE
100views Hardware» more  DATE 2005»
13 years 9 months ago
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application
Developing a functional prototype of a system-on-chip provides a unifying vehicle for model validation and system refinement. Keeping the prototype executable everal abstraction l...
Alexandre Chureau, Yvon Savaria, El Mostapha Aboul...
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
14 years 1 months ago
Divide and concatenate: a scalable hardware architecture for universal MAC
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
Bo Yang, Ramesh Karri, David A. McGrew
DFT
2005
IEEE
64views VLSI» more  DFT 2005»
14 years 1 months ago
Implementation of Concurrent Checking Circuits by Independent Sub-circuits
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
Vladimir Ostrovsky, Ilya Levin
MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
14 years 2 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill