1013 search results - page 32 / 203 » A hardware implementation of realloc function |
CAV
2010
Springer
13 years 11 months ago
2010
Springer
For efficiency and portability, network packet processing code is typically written in low-level languages and makes use of bit-level operations to compactly represent data. Althou...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
— To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scal...
IOLTS
2000
IEEE
14 years 6 days ago
2000
IEEE
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. Th...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation ...
ARC
2007
Springer
13 years 11 months ago
2007
Springer
Many important algorithms in computational biology and related subjects rely on the ability to extract and to identify sub-graphs of larger graphs; an example is to find common fun...