Self-Testing of FPGA Delay Faults in the System Environment

We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. This improvement is obtained by modifying the functions of LUTs in the section under test, so that each LUT implements a XOR function. We show that, despite many potential problems, the proposed modification can significantly enhance the susceptibility of FPGA delay faults to random testing.

• Type: Conference
• Year: 2000
• Where: IOLTS
• Authors: Andrzej Krasniewski
• Keywords: FPGA Delay Faults, Hardware, IOLTS 2000, Procedure, User-defined Function