1013 search results - page 66 / 203 » A hardware implementation of realloc function |
FPL
2009
Springer
14 years 16 days ago
2009
Springer
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
EH
2002
IEEE
14 years 26 days ago
2002
IEEE
The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occ...
MICRO
2000
IEEE
14 years 9 days ago
2000
IEEE
Current superscalar microprocessors’ performance depends on its frequency and the number of useful instructions that can be processed per cycle (IPC). In this paper we propose a...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents a novel architecture for on-chip neural network training using particle swarm optimization (PSO). PSO is an evolutionary optimization algorithm with a growing ...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...