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ITC
1995
IEEE
104views Hardware» more  ITC 1995»
13 years 11 months ago
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
Nur A. Touba, Edward J. McCluskey
ICCAD
2007
IEEE
115views Hardware» more  ICCAD 2007»
14 years 4 months ago
Timing optimization by restructuring long combinatorial paths
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
Jürgen Werber, Dieter Rautenbach, Christian S...
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 2 months ago
A Generic Standard Cell Design Methodology for Differential Circuit Styles
In this paper we present a generic methodology for the rapid generation and implementation of standard cell libraries for differential circuit design styles. We demonstrate a syst...
Stéphane Badel, Erdem Guleyupoglu, Ozgur In...
ISCAS
2007
IEEE
164views Hardware» more  ISCAS 2007»
14 years 2 months ago
Noise Figure Measurement Using Mixed-Signal BIST
—A Built-In Self-Test (BIST) approach for functionality measurements, including noise figure (NF), linearity and frequency response of analog circuitry in mixedsignal systems, is...
Jie Qin, Charles E. Stroud, Foster F. Dai
ARC
2007
Springer
119views Hardware» more  ARC 2007»
14 years 2 months ago
Authentication of FPGA Bitstreams: Why and How
Abstract. Encryption of volatile FPGA bitstreams provides confidentiality to the design but does not ensure its authenticity. This paper motivates the need for adding authenticati...
Saar Drimer