1013 search results - page 8 / 203 » A hardware implementation of realloc function |
CHES
2007
Springer
14 years 1 months ago
2007
Springer
This paper describes a new compression function, MAME designed for hardware-oriented hash functions which can be used in applications reduced hardware requirements. MAME takes a 25...
ISMVL
2000
IEEE
14 years 4 days ago
2000
IEEE
A sequential realization of multiple-output logic functions is presented. A conventional sequential realization is based on SBDDs (Shared reduced ordered Binary Decision Diagrams)...
EH
1999
IEEE
1999
IEEE
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
14 years 2 days ago
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
GECCO
2005
Springer
14 years 1 months ago
2005
Springer
Genetic Algorithms (GAs) are very commonly used as function optimizers, basically due to their search capability. A number of different serial and parallel versions of GA exist. ...