1013 search results - page 93 / 203 » A hardware implementation of realloc function |
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
We propose signature-accelerated transactional memory (SigTM), a hybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the r...
ICIP
2007
IEEE
14 years 2 months ago
2007
IEEE
Practical sparse approximation algorithms (particularly greedy algorithms) suffer two significant drawbacks: they are difficult to implement in hardware, and they are inefficie...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
ASPDAC
1999
ACM
14 years 9 days ago
1999
ACM
This paper presents a performance-driven I/O pin routing algorithm with special consideration of wire uniformity. First, a topological routing based on min-cost max-flow algorith...
DAC
1999
ACM
14 years 9 days ago
1999
ACM
This paper presents a design methodology, called common-case computation (CCC), and new design automation algorithms for optimizing power consumption or performance. The proposed ...