17 search results - page 2 / 4 » A hardware redundancy and recovery mechanism for reliable sc... |
DSN
2006
IEEE
14 years 1 months ago
2006
IEEE
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
EUROMICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
BPEL is the de facto standard for business process modeling in today's enterprises and is a promising candidate for the integration of business and scientific applications tha...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing o...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...