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DFT
2003
IEEE
142views VLSI» more  DFT 2003»
14 years 21 days ago
Exploiting Instruction Redundancy for Transient Fault Tolerance
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
Toshinori Sato
HPDC
2008
IEEE
14 years 1 months ago
StoreGPU: exploiting graphics processing units to accelerate distributed storage systems
Today Graphics Processing Units (GPUs) are a largely underexploited resource on existing desktops and a possible costeffective enhancement to high-performance systems. To date, mo...
Samer Al-Kiswany, Abdullah Gharaibeh, Elizeu Santo...
HPDC
2010
IEEE
13 years 8 months ago
A data transfer framework for large-scale science experiments
Modern scientific experiments can generate hundreds of gigabytes to terabytes or even petabytes of data that may furthermore be maintained in large numbers of relatively small fil...
Wantao Liu, Brian Tieman, Rajkumar Kettimuthu, Ian...
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 1 months ago
Low-cost protection for SER upsets and silicon defects
Extreme transistor scaling trends in silicon technology are soon to reach a point where manufactured systems will suffer from limited device reliability and severely reduced life...
Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kyp...
MICRO
2008
IEEE
114views Hardware» more  MICRO 2008»
14 years 1 months ago
Toward a multicore architecture for real-time ray-tracing
Significant improvement to visual quality for real-time 3D graphics requires modeling of complex illumination effects like soft-shadows, reflections, and diffuse lighting intera...
Venkatraman Govindaraju, Peter Djeu, Karthikeyan S...