Sciweavers

70 search results - page 3 / 14
» A hardware software partitioning algorithm for pipelined ins...
Sort
View
FPL
2010
Springer
267views Hardware» more  FPL 2010»
13 years 4 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch
VLSID
1999
IEEE
139views VLSI» more  VLSID 1999»
13 years 11 months ago
Processor Modeling for Hardware Software Codesign
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
V. Rajesh, Rajat Moona
ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
14 years 3 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome
FPL
2004
Springer
95views Hardware» more  FPL 2004»
13 years 12 months ago
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor
Abstract. This paper proposes an architecture that combines a contextswitching virtual configware/software SAT solver with an embedded processor to promote a tighter coupling betwe...
C. J. Tavares, C. Bungardean, G. M. Matos, Jos&eac...
ASAP
2005
IEEE
133views Hardware» more  ASAP 2005»
14 years 6 days ago
Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware
In this paper, we propose a hardware/software partitioning method for improving applications’ performance in embedded systems. Critical software parts are accelerated on hardwar...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...