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ERSA
2006
133views Hardware» more  ERSA 2006»
13 years 9 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang
CODES
2005
IEEE
14 years 1 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
CF
2004
ACM
14 years 1 months ago
The digital divide of computing
This presentation urges for creating more awareness of the impact of configware engineering onto embedded system development and examines the requirements of overdue CSE curricula...
Reiner W. Hartenstein
EMSOFT
2005
Springer
14 years 1 months ago
A unified HW/SW interface model to remove discontinuities between HW and SW design
One major challenge in System-on-Chip (SoC) design is the definition and design of interfaces between hardware and software. Traditional ASIC designer and software designer model ...
Aimen Bouchhima, Xi Chen, Frédéric P...
CODES
2003
IEEE
14 years 28 days ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa