7 search results - page 1 / 2 » A hierarchical three-way interconnect architecture for hexag... |
SLIP
2003
ACM
14 years 4 months ago
2003
ACM
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
ICCD
2002
IEEE
14 years 7 months ago
2002
IEEE
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
DFT
2003
IEEE
14 years 4 months ago
2003
IEEE
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori connected mESHes (TESH)". The major features of TESH are the following: it i...
FCCM
2007
IEEE
14 years 5 months ago
2007
IEEE
A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is ...
ISCA
2006
IEEE
13 years 11 months ago
2006
IEEE
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...