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DATE
2000
IEEE
139views Hardware» more  DATE 2000»
15 years 10 months ago
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
USENIX
2004
15 years 7 months ago
Making the "Box" Transparent: System Call Performance as a First-Class Result
For operating system intensive applications, the ability of designers to understand system call performance behavior is essential to achieving high performance. Conventional perfo...
Yaoping Ruan, Vivek S. Pai
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
15 years 10 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
HPCC
2007
Springer
16 years 10 days ago
Optimizing Array Accesses in High Productivity Languages
One of the outcomes of DARPA’s HPCS program has been the creation of three new high productivity languages: Chapel, Fortress, and X10. While these languages have introduced impro...
Mackale Joyner, Zoran Budimlic, Vivek Sarkar
ICSE
2005
IEEE-ACM
16 years 6 months ago
Main effects screening: a distributed continuous quality assurance process for monitoring performance degradation in evolving so
Developers of highly configurable performanceintensive software systems often use a type of in-house performance-oriented "regression testing" to ensure that their modif...
Cemal Yilmaz, Arvind S. Krishna, Atif M. Memon, Ad...