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ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
14 years 1 months ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
LCN
1998
IEEE
13 years 12 months ago
High Performance Integrated Network Communications Architecture (INCA)
Current communication subsystem mechanisms within workstation and PC class computers are limiting network communications throughput to a small percentage of the present network da...
Klaus Schug, Anura P. Jayasumana, Prasanth Gopalak...
ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
14 years 4 months ago
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
14 years 1 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton