Sciweavers

2209 search results - page 22 / 442
» A high performance JPEG2000 architecture
Sort
View
TVLSI
2008
164views more  TVLSI 2008»
13 years 7 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
CHES
2000
Springer
167views Cryptology» more  CHES 2000»
13 years 12 months ago
A High Performance Reconfigurable Elliptic Curve Processor for GF(2m)
This work proposes a processor architecture for elliptic curves cryptosystems over fields GF(2m ). This is a scalable architecture in terms of area and speed that exploits the abil...
Gerardo Orlando, Christof Paar
DELTA
2008
IEEE
14 years 2 months ago
High Performance FPGA Implementation of the Mersenne Twister
Efficient generation of random and pseudorandom sequences is of great importance to a number of applications [4]. In this paper, an efficient implementation of the Mersenne Twis...
Shrutisagar Chandrasekaran, Abbes Amira
DAC
2001
ACM
14 years 8 months ago
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed an...
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, L...
SIGGRAPH
1994
ACM
13 years 11 months ago
IRIS performer: a high performance multiprocessing toolkit for real-time 3D graphics
This paper describes the design and implementation of IRIS Performer, a toolkit for visual simulation, virtual reality, and other real-time 3D graphics applications. The principal...
John Rohlf, James Helman