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» A high performance JPEG2000 architecture
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ICCD
2007
IEEE
132views Hardware» more  ICCD 2007»
14 years 4 months ago
Post-layout comparison of high performance 64b static adders in energy-delay space
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
Sheng Sun, Carl Sechen
CLUSTER
2008
IEEE
14 years 2 months ago
Context-aware address translation for high performance SMP cluster system
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...
Moon-Sang Lee, Joonwon Lee, Seungryoul Maeng
VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
14 years 8 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
DAC
1996
ACM
13 years 11 months ago
Sizing of Clock Distribution Networks for High Performance CPU Chips
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
Madhav P. Desai, Radenko Cvijetic, James Jensen
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
14 years 29 days ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas