2209 search results - page 31 / 442 » A high performance JPEG2000 architecture |
ISCC
2005
IEEE
14 years 1 months ago
2005
IEEE
—A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optim...
ARITH
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...
ICMCS
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
SBACPAD
2008
IEEE
14 years 2 months ago
2008
IEEE
Single processor technology has been evolving across last decades, but due to physical limitations of chip manufacturing process, the industry is pursuing alternatives to sustain ...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...